Design-Reuse

Optimization Methodologies for Cycle-Accurate SystemC Models Converted from RTL VHDL

IP design-houses are hard-pressed by their customers to provide SystemC models of their portfolio IPs, despite already existing VHDL views. VHDL IPs can be translated to SystemC, ensuring correctness, ...
TechRepublic

VHDL Implementation of 8-Bit ALU

In this paper VHDL implementation of 8-bit Arithmetic Logic Unit (ALU) is presented. The design was implemented using VHDL Xilinx Synthesis tool ISE 13.1 and targeted for Spartan device. ALU was ...
Hackaday

Simulating VHDL Of An AVR8 Soft Processor

Okay, now we’re beginning to feel a bit like [Alice]. This tutorial shows you how to simulate VHDL code. This code is intended to run on an FPGA and includes a software-only version of the AVR 8-bit ...
TechRepublic

Structural VHDL Implementation of Wallace Multiplier

Scheming multipliers that are of high-speed, low power, and standard in design are of substantial research interest. By reducing the generated partial products speed of the multiplier can be increased ...
Semiconductor Engineering

Improving VHDL

For the past several years, I have had the privilege to chair the IEEE 1076 VHDL working group. In March, we handed off the revisions to the VHDL LRM to our technical editor to finalize the document ...
EDN

VHDL, Verilog models available for Spansion flash

SAN FRANCISCO — Free Model Foundry (FMF), an open source model warehouse and design services company promoting development and distribution of simulation models of electronic components, announced ...